The present embodiments relate to integrated circuits and, more particularly, to integrated circuits with circuitry that transposes two-dimensional arrays.
Generating the transpose of a two-dimensional array having M rows and N columns involves swapping the rows of the two-dimensional array (e.g., a matrix A) with the columns of the transpose of the two-dimensional array (e.g., the transposed matrix AT) or the columns of the two-dimensional array (e.g., matrix A) with the rows of the transposed two-dimensional array (e.g., matrix AT). Thus, the transpose of a matrix A with M rows and N columns is a matrix AT with N rows and M columns. In other words, an element from row i and column j of matrix A (i.e., Aij) becomes an element in row j and column i of the transposed matrix AT (i.e., ATji).
Generating the transpose of a matrix has many applications in linear algebra including the commutativity of scalar multiplications, which is sometimes also referred to as the computation of the dot product, and the computation of the inverse of the two-dimensional array. For example, the dot product (Au).v where A is a matrix with M rows and N columns, u is an N-dimensional vector, and v an M-dimensional vector can be rewritten as u.(ATv) where AT has N rows and M columns and is the transpose of matrix A.
By way of further preliminaries, it will be understood that throughout this disclosure all “data,” “samples,” “items,” “inputs,” “outputs,” “values,” “addresses,”, “difference”, “sum” and/or the like that are referred to are represented by electrical signals that are processed by electronic circuitry. Thus references to “data,” “samples,” “items,” “inputs,” “outputs,” “values,” “addresses,”, “difference”, “sum” and/or the like herein will be understood to always mean “data signals,” “sample signals,” and/or the like, even though the word “signal” or “signals” may not be expressly stated in all instances.